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Checked - no significant difference at pause, low volume (-35dB) and high (0dB).
AVDD17 or 27? I think 17 is the line out and mixer, 27 is the headphone.
Testing CVDD2, it seems that PVDD1 is derived from it
rockbox-backlight.patch: disable DCDC15 when screen off (save 1mA), like we already do in Clip Plus. Good for inclusion in main branch.
is that so special to the Clip Zip, or is it easy to adapt to other Sansa devices?
Current git + 1.1v CPU (no change to other clocks): 15h 0min
Quote from: oid_maps on September 29, 2014, 03:07:45 PMis that so special to the Clip Zip, or is it easy to adapt to other Sansa devices?I suppose we need check each device for optimal frequency/voltage for best result and stability, but it should by mostly same. In any case at first we should check and fix frequency scaling and push it in to main branch. Then we can adapt it to other device.
Quote from: saratoga on September 29, 2014, 01:38:52 PMCurrent git + 1.1v CPU (no change to other clocks): 15h 0minIs 1.1V lower stable voltage on 240Mhz?
Quote from: Mihail Zenkov on September 29, 2014, 03:32:26 PMQuote from: oid_maps on September 29, 2014, 03:07:45 PMis that so special to the Clip Zip, or is it easy to adapt to other Sansa devices?I suppose we need check each device for optimal frequency/voltage for best result and stability, but it should by mostly same. In any case at first we should check and fix frequency scaling and push it in to main branch. Then we can adapt it to other device.I was about the backlight-patch. I thought that it was clear because I cited just that part.
I try new solution - don't switch PCLK. In this case at normal frequency we have FCLK 40MHz / PCLK 20MHz, at boost - FCLK 240MHz / PCLK 120MHz.
Are you sure about that?
Max PCLK is 60 MHz IIRC, and when we tested, raising PCLK increased power consumption a lot more than raising FCLK (because many things on the chip also increase in frequency).
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