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Do we use the ide interface at all for the ams sansas? I'm trying to understand why the ide interface gets enabled and clocked in sd_init. I thought the internal sd was on the nand interface and the microsd was on the sd/mmc interface, connected to the processor through the apb/ahb bus. Does the ide interface need to be enable for some reason? DRAM? What's the connection here?
If we run the processor at less than 200 MHz, the core voltage can be reduced from 1.2V to 1.1V, according to the as3525 datasheet (see the note in paragraph 6.2.2) . This could save some power (in a simple approximation dissipated power is inversely proportional to the *square* of the voltage). I think we don't really *need* to run at absolute maximum speed of 248 MHz, so we could save power by running slightly lower than 200 MHz.
By the way, I noticed that AMS has a new revision (rev1.13) of the as3525 datasheet on their website, see http://www.austriamicrosystems.com/eng/Products/Mobile-Entertainment/High-Performance-Microcontrollers
You really should make the full speed available while boosted, I'd imagine. Otherwise you're potentially cutting off file formats (ApeV2 at certain compression levels possibly) as well as restricting the bitrates and possibly resolutions at which video can be encoded.The whole point of being boosted is that things that need a large amount of CPU can get the full capabilities of the player behind them.If there's a role for "not quite full power" it should probably be engineered in as a general thing, rather than choosing to limit just one port (well, set of ports).
If we run the processor at less than 200 MHz, the core voltage can be reduced from 1.2V to 1.1V, according to the as3525 datasheet (see the note in paragraph 6.2.2) . This could save some power (in a simple approximation dissipated power is inversely proportional to the *square* of the voltage). I think we don't really *need* to run at absolute maximum speed of 248 MHz, so we could save power by running slightly lower than 200 MHz
Ah yes found it now.Does this note on the next page under 6.2.3 have any bearing on this lower frequency?(1) This setting must not be used for AS3525 core supply because the lower voltage limit is out of core supply specification limits.EDIT: I suppose this could apply for the above 200Mhz clocking and if we're below that the note on the previous page would apply. Otherwise why would there be a setting for lower?
On a slightly different clocking issue, the ARM922 tech ref (para 5.4) says that for asynch mode, FCLK must have a higher frequency than BCLK. But without boost, Rockbox seems to run FCLK at 31MHz & BCLK (aka HCLK in the AS3525) at 62MHz. How does Rockbox get away with that?
Regarding DBOP clocking, is this code CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ);in ams3525_dbop_init() correct?
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