Rockbox Development > New Ports
SanDisk Sansa c200v2, m200v4, clipv1, clipv2, clip+, and fuzev2
funman:
Ok so using 82.666MHz clock for IDE shows better results than with 62MHz
The OF seems to use 64MHz (384/6) , if we want to see if it works alright with 64MHz, we need to change the PLLA setting to a multiple of 64MHz. (like 384MHz)
If you don't know how to change it (you need to modify the PLLA setting!) I'll try to come with a patch tomorrow.
Thanks for testing!
iudex:
So, what's now to do?
saratoga:
I put a list of requirements we'd agreed on informally for a release on the wiki page. Of course those are just the minimum for a release, theres much more then that left undone.
FlynDice:
Ok, here's the second go at something to show what the clocked rates are. Tell me if you think this should go on FS as a patch or if this is ok just attaching to a post. This patch only assumes that clk_main = 24 MHz. Everything else is calculated using the actual dividers read from registers. It takes into account synchronous, asynchronous, fastbus, optional clock inputs and seems to work very well for me. The layout may stretch a bit long vertically for the fuze but it fits nicely in the e200 screen.
funman:
--- Quote from: funman on May 17, 2009, 09:58:41 AM ---If you don't know how to change it (you need to modify the PLLA setting!) I'll try to come with a patch tomorrow.
--- End quote ---
I couldn't make a patch with 64MHz freq for pclk which booted on my Fuze (showed a white screen), so I suggest just reverting this with a comment.
test_disk with CGU_IDE at 90MHz (real : 82.66MHz) just passes, so unless someone else has an idea..
@FlynDice : if you can make your patch scroll in both directions (think of the Clip..) it should be committed
EDIT: I added FS#10216 to fix possible ATA problems on 8GB models, but it requires testing by a owner of such a device. wpyh?
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