Rockbox Development > New Ports
SanDisk Sansa c200v2, m200v4, clipv1, clipv2, clip+, and fuzev2
atomikpunk:
Hi Michael,
thanks for the cheers ;D
About the memory mapping, Bagder will be the one who can answer this question since he's the one who worked out an arrangement with Austriamicrosystems. He will be able to release selected information based on his agreement.
If you are interested in helping understanding the OF, let me know and I will be able to share what I already found about it. And maybe we will be able to divide work and cooperate (via IRC/Wiki/Forums?).
daniel_at:
Hi again,
Okay so far I have just opened it and made some pictures of it. You can find it at flicker here:
http://flickr.com/photos/90053035@N00/sets/72157605072639496/
I have added notes to some of the pictures, but they dont show up in opera... but the bottom-note says there are comments in it.
For the switches: I just made some measurements - no deep insights so far. All switches seem to be connected to a resistor-network (with 2 R's for each switch), except the Pwr-switch. All switches (again except the Pwr) are connected to Digital (or Power-)GND on one side. The other side is connected to a pulled-up line to about 3V, which switches off (or goes high-Z) every 0.5ms for a very short period of time. But the intervall between the shutoffs is not _very_ periodical and depends on task running on the E200 (so it seems to be handled in an low-priority scheduled thread).
The pulled-Up line goes to about 0.3V if the display-background light is off (i.e. powersaving mode) EXCEPT for the "UP" (or play) Switch (not the wheel-up). Maybe this is somehow a "special" key which can be checked by GPIO.
But my guess is, that all keys trigger a GPIO and than the level is checked by the ADC (maybe therefore the "high-Z" spikes).
I cant even say, if there is only one common signal line for the switches which goes to the SoC (but it pretty seems so)
HTH a bit,
Daniel
But these assumptions are very rough guesses - i havent spent much time so far on it.
I also tried (just by random poke'in) to find one of the vias near the SoC which carrys the common signal for the swtches... but havent found one...
Bagder:
For lots of info on the AS3525 like (default) memory addresses for various things, check the attached patch to tracker entry FS#8843:
http://www.rockbox.org/tracker/task/8843
It is supposedly based on the AS3525 Linux patch and does include lots of details otherwise only mentioned in the data sheet.
atomikpunk:
Just for the records before I go to bed, I did some investigation and found some info about which memory ranges are in use. All my findings applies to the M200 series, but it should be pretty easy to translate it to other models. The range 0x49C60 to 0x4A060 seems to be used for stack, while the TTB is located at 0x44000 (up to 0x4BFFF). I found out where the TTB and TLBs are setup and I hope to better understand the memory usage, and eventually find out how libraries are loaded in memory and how they are used in the firmware.
daniel_at:
@Bagder: You have some datasheets for the AS3525 - or?
Do these give some information about the/a JTAG interface to the SoC/or the integrated uC?
I wanted to try to find out if the on-board 8-pin connector is a JTAG-interface and if so, also get the pin-assignment of it. So far i know:
1 - GND
2 - low-active reset (pull to GND to reset)
3 - high-Z, pulled up
4 - high-Z, pulled up
5 - high-Z, pulled up
6 - high-Z, pulled up
7 - high-Z, pulled up
8 - V+ (3.3V)
(Pin1 is a rectangular pad...others are oval)
This means that there is one line to much for JTAG, maybe one of them has to be pulled low to enable JTAG. Does the datasheet say something about it? And has the uC in Reset-mode? (I dont think so - or?)
I have added some pics: http://flickr.com/photos/90053035@N00/2496093231/in/set-72157605072639496/
If we get JTAG working and get r/w access to the flash, than testing would be a lot easier, bec. we could always unbrick it.
Daniel
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