Thank You for your continued support and contributions!
ldr r0, [r7] @ r7 points to the acmd41 command response, so r0 contains the responseasrs r1, r0, 31 @ if the bit 31 was set (meaning card ready), now r1 == 0xffffffffadds r1, #1 @ if the bit 31 was set, now r1 == 0beq card_ready @ if the bit 31 was set, branch to card_ready...card_ready:lsls r0, r0, #8lsrs r0, r0, #8 @ clears the 8 most significative bitsstr r0, [r4, #0x14] @ store the result in memory (it indicates the supported voltages)ldr r0, [r4, #0x8]
offset - value when acmd41 succeeded - (value when 1st call returned if different) - comment00 C8000000 @ pl180 controller base04 3D09000 = 64000000 = clock reference (64MHz, probably CGU_PERI)08 0 @ card selected (value written in MCI_SELECT)0C 010 1 (0)14 0xFF8000 @ the supported voltages18 6429 (0) @ a function called at various places in the init function1C 45E9 (0) @ the command response handler (it is the init function itself)20 - 24 : 028 0 @ another function, always set to 0 (NULL)2C 4 (0)30 400 (0)34 3 @ the clock divider for "high" frequency of 20MHz (64/20 == 3)38 - 44 : 048 0 @ here it's weird, it should always be set to 1, and this value -1 is written into MMC_SELECT, not sure why it's 0 there (to analyze)4C - 60 : 064 1068 - 74 : 078 4D (0) @ the loop counter for acmd41 (starts at 0x50, decremented each time acmd41 fails, abort when it reaches 0)7C 1FF 80 1FF @ I'm not sure, but it corresponds to the maximum clock divider we can use in MMC_CLOCK (511 == 255*2 + 1)84 - A4 : 0A8 8 (1) @ The status of the card in the intialisation (detailed after) , here means we were reading the acmd41 answerAC 1 (0xffffffff)B0 - D0 : 0D4 1 (0) @ To check carefully, at some point, thevalue 1 seems to mean SD (as opposed to MMC), but it is set to 2 and 0 as well .. quite a few branches depend on it, to investigateD8 0 @ Indicates if the card is SDHC or notDC - E8 : 0
Page created in 0.108 seconds with 20 queries.