Rockbox Development > New Ports
SanDisk Sansa c200v2, m200v4, clipv1, clipv2, clip+, and fuzev2
funman:
unsurprisingly the error is in set_cpu_frequency() which is known to be buggy.
If you force the CPU to always be at maximum (in debug menu -> cpu frequency; set the counter to 1 or more), it shouldn't happen anymore.
Timar:
Great, that solved the problem... thanks! So I guess the older builds run stable because they don't have that feature?
Is there any way to save that setting into a cfg file to default it on startup?
funman:
--- Quote from: Timar on April 19, 2010, 03:01:36 PM ---Is there any way to save that setting into a cfg file to default it on startup?
--- End quote ---
No.
ranma:
Did some power draw measurements on my C200v2 today:
OF:
--- Quote ---Playing mp3, display off:
3.85V, 28mA
Playing mp3, display full brightness, buttonlights on:
3.80V, 68mA
--- End quote ---
rockbox:
--- Quote ---Not playing, settings menu, display full brightness, main buttonlight on:
3.79V, 64mA (Not 68mA because 'menu' light is off I suppose)
Not playing, settings menu, display full brightness, main buttonlight off:
3.81V, 51mA
Not playing, settings menu, display off, buttonlights off:
3.84V, 34mA
Playing mp3, now playing screen, display full brightness, main buttonlight on:
3.76V, 78mA
Playing mp3, now playing screen, display full brightness, main buttonlight off:
3.78V, 65mA
Playing mp3, now playing screen, display off, main buttonlight off:
3.81V, 48mA
--- End quote ---
[edit]
At funmans suggestion I did a readout of the ascodec state on
both original firmware and rockbox:
--- Code: ------ originalfirmware.ascodec.readout.txt 2010-04-21 23:00:48.868252431 +0900
+++ rockbox.ascodec.readout.txt 2010-04-21 23:00:37.391522447 +0900
@@ -1,9 +1,9 @@
0x00: 00000000
0x01: 00000000
-0x02: 00000003
-0x03: 00000043
+0x02: 000000c5
+0x03: 00000045
0x04: 00000000
-0x05: 00000000
+0x05: 00000080
0x06: 00000000
0x07: 00000000
0x08: 00000000
@@ -12,15 +12,15 @@
0x0b: 00000000
0x0c: 00000000
0x0d: 00000000
-0x0e: 00000019
-0x0f: 00000059
+0x0e: 00000016
+0x0f: 00000056
0x10: 00000000
0x11: 00000000
0x12: 00000000
0x13: 00000000
0x14: 00000060
-0x15: 0000003f
-0x16: 00000006
+0x15: 00000007
+0x16: 00000000
0x17: 00000000
0x18: 00000000
0x19: 00000000
@@ -30,22 +30,22 @@
0x1d: 00000000
0x1e: 00000000
0x1f: 00000000
-0x20: 00000031
-0x21: 00000016
-0x22: 0000005c
-0x23: 0000000b
+0x20: 00000039
+0x21: 00000004
+0x22: 00000081
+0x23: 00000000
0x24: 00000000
0x25: 00000000
0x26: 00000010
-0x27: 00000001
-0x28: 000000f3
+0x27: 00000030
+0x28: 00000023
0x29: 00000040
-0x2a: 000000b7
-0x2b: 00000043
+0x2a: 00000092
+0x2b: 00000042
0x2c: 0000008b
0x2d: 00000035
0x2e: 00000002
-0x2f: 000000f5
+0x2f: 000000f7
0x30: 00000000
0x31: 00000000
0x32: 00000000
--- End code ---
Main differences are as follows, I'd guess at most the bias current and load setting changes would make a difference in power draw:
--- Quote ---0x02: (HPH_OUT_R)
OF: 0x03: [edit]Overcurrent timeout 256ms[/edit]
RB: 0xc5: 'Do not change, default 0' bit is set to 1[edit]Overcurrent timeout 0ms[/edit]
0x05: (SPH_OUT_L)
OF: 0x00: output normal
RB: 0x80: output muted (power up default)
0x15: (AudioSet_2)
OF: 0x3f: Bias current reduction 50%, AGC disabled
RB: 0x07: No bias current reduction, AGC enabled
0x16: (AudioSet_3)
OF: 0x06: 32 Ohm load or more, cm buffer on, zero cross update disabled
RB: 0x00: 16 Ohm load, cm buffer on, zero cross update enabled
0x20: (System)
OF: 0x31: PVdd unreduced
RB: 0x39: PVdd Vnom*17/18
0x21: (DCDC3)
OF: 0x16: BVDD 3.1V CVDD 1.1V
RB: 0x04: BVDD 3.6V CVDD 1.2V (probably halted it in boost mode?)
0x22: (Charger) [Was not plugged in in both cases, running on battery]
OF: 0x5c: NTC supply on, 100mA, 4.2V, charger enabled
RB: 0x81: NTC supply off, charger disabled
0x23: (DCD15)
OF: 0x0b: 13.75mA [Well, this regulator should be unused, maybe dead code in OF?]
RB: 0x00: off
0x28: (RTCV)
OF: 0xF3: Supply 2.5V
RB: 0x23: Supply 1.2V
--- End quote ---
[/edit]
[edit2]
I just noticed that the rockbox current draw values might be completely off,
I measured them with a local patch that may have caused BVDD to stay
on the boost value...
No, for one thing it's CVDD, the BVDD 3.6V thing shouldn't really come into play until the battery is nearly empty.
And the voltage scaling code does not get compiled in AFAICS, so it just stays at 1.2V CVDD.
Still the additional current due to higher CVDD shouldn't be too big, I'd expect about 20% increase (1.2^2/1.1^2).
The difference I measured here is more like 70%...
[/edit2]
funman:
Thanks!
I'll try a bench with modified audioset2 and audioset3 to see if it changes anything. no change
You have dumped CGU registers already, now the only difference I can think of is in GPIO registers ? Can you dump and GPIO_DIR (+0x400) and GPIO_DATA (+0x0) ?
This could give a clue at how c200v2 power is drawn if some PIN is set, but hopefully we could identify the code using it in the OF and compare with other models.
Oh well I remember some code which put SDRAM in self-refresh mode, and most of the audio codecs are loaded in IRAM, so the SDRAM could be disabled (I don't know if this can account for high power usage)
The datasheet for the SDRAM chip (linked from wiki SansaC200v2) has current values page 4, but i'm not sure which one apply (I suppose the correct value is weighted from all of them)
In OF, 0x301C enters self refresh mode (next function leaves the mode), parent 0x1CD8 is called multiple times (I have not identified callers though)
In your post I see that external memory clocks are enabled when playing mp3, perhaps it's enabled/disabled at some high frequency?
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