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Setting PCLK to 64MHz fixes the problem on my Clipv2.
Edit: Heres a Fuze v2 build with the lower clock. Would also be interesting to know if this one works:
Constant CVDD1:http://web.mit.edu/mgg6/www/rockbox-fuzev2.7z
If I understood right, fuze v2 have problem only when boost = 0.
Looking at the as3525 datasheet, I think we are clocking the DBOP too high due to increased PCLK, and the DBOP is accessed during LCD update, so lets try lowering it:http://web.mit.edu/mgg6/www/rockbox-fuzev2_2.7z
Setting PCLK to 64MHz fixes the problem on my Clipv2. Edit: Heres a Fuze v2 build with the lower clock. Would also be interesting to know if this one works:http://web.mit.edu/mgg6/www/rockbox-fuzev2_64MHz.7z
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