Thank You for your continued support and contributions!
CGU_PERI &= ~0x7f should be alright for i2c, I am not too sure about DBOP since now we run it at 62MHz. Perhaps we'll need to modify the timing registers.
> halttarget state: haltedtarget halted in ARM state due to debug-request, current mode: Supervisorcpsr: 0x60000053 pc: 0x00000084MMU: disabled, D-Cache: disabled, I-Cache: disabled> arm disassemble 0x70 6 0x00000070 0xe59f0164 LDR r0, [r15, #0x164]0x00000074 0xe3a01000 MOV r1, #0x00x00000078 0xe5801400 STR r1, [r0, #0x400]0x0000007c 0xe5901100 LDR r1, [r0, #0x100]0x00000080 0xe3510000 CMP r1, #0x00x00000084 0x0afffffe BEQ 0x00000084> reg r0r0 (/32): 0xC80D0000> mdw phys 0xC80F0000 0x200xc80f0000: 00002630 00006a2f 00000000 00000008 00000051 0f810000 0000010d 000000110xc80f0020: 00000001 00000001 00000020 00000020 000000cd 00000191 00000000 000000000xc80f0040: 00002630 00006a2f 00000000 00000008 00000051 0f810000 0000010d 000000110xc80f0060: 00000001 00000000 00000020 00000020 000000cd 00000191 00000000 00000000
Can you post a patch (without DBOP modifications since it's unrelated) on flyspray so we can test on each model before committing ?
thanks! i committed it for c200v2 only, I'll try on my devices so we can remove the USB pin and use this code on all devices.
static inline void delay(void) { int i = 40; while(i--) ; }void mod_cgu (void){ max_div_peri = ((peri_setting >> 2) & 0xf) + 1; min_div_proc = ((proc_setting >> 4) & 0xf) + 1; div_proc = min_div_proc * max_div_peri; if(div_proc > 0xf) div_proc = 0xf; if(min_div_proc > 0xf) min_div_proc = 0xf; CGU_PROC = (proc_setting & 0xf) | ((div_proc - 1) << 4); delay(); int div_peri = 1; /* * pclk: faster -> slower * fclk: slower -> faster */ while(div_proc > min_div_proc && div_peri < max_div_peri) { if(div_peri < max_div_peri) { CGU_PERI_DIV = div_peri; /* bits 7:2 */ delay(); div_peri++; } if(div_proc > min_div_proc) { CGU_PROC_DIV = (div_proc - 2); /* bits 7:4 */ delay(); div_proc--; } }}
Perhaps B5 is to select internal/µSD ?
I don't remember seeing a different base address like (there are 2 PL180 controllers in the AS3525v1), and MCI_HCON only reports 1 card present.
BTW 0x0000XXXX is correct for RCA, it is a 16 bits register.
Quote from: funman on March 13, 2010, 05:48:43 AMBTW 0x0000XXXX is correct for RCA, it is a 16 bits register.But the RCA is the 16 MSB and if it sends 0x0000XXXX then it's using an RCA of 0x0000 which is not going to work for the SD_SELECT_CARD cmd. Using an RCA of 0 for the SD_SELECT_CARD cmd actually deselects the card.
30200f08 <memset16>:30200f08: e3100002 tst r0, #2 ; 0x230200f0c: 13520000 cmpne r2, #0 ; 0x030200f10: 10c010b2 strneh r1, [r0], #230200f14: 12422001 subne r2, r2, #1 ; 0x130200f18: e1811801 orr r1, r1, r1, lsl #1630200f1c: e1a03001 mov r3, r130200f20: e3520008 cmp r2, #8 ; 0x830200f24: ba00000f blt 30200f68 <memset16+0x60>30200f28: e52de004 str lr, [sp, -#4]!30200f2c: e1a0c001 mov ip, r130200f30: e1a0e001 mov lr, r130200f34: e2522020 subs r2, r2, #32 ; 0x2030200f38: a8a0500a stmgeia r0!, {r1, r3, ip, lr}30200f3c: a8a0500a stmgeia r0!, {r1, r3, ip, lr}30200f40: a8a0500a stmgeia r0!, {r1, r3, ip, lr}30200f44: a8a0500a stmgeia r0!, {r1, r3, ip, lr}
> arm disassemble 0x30200f08 160x30200f08 0xe3100002 TST r0, #0x20x30200f0c 0x13520000 CMPNE r2, #0x00x30200f10 0x00000000 ANDEQ r0, r0, r00x30200f14 0x12422001 SUBNE r2, r2, #0x10x30200f18 0xe1811801 ORR r1, r1, r1, LSL #0x100x30200f1c 0xe1a03001 MOV r3, r10x30200f20 0x00000000 ANDEQ r0, r0, r00x30200f24 0xba00000f BLT 0x30200f680x30200f28 0xe52de004 STR r14, [r13, #-0x4]!0x30200f2c 0xe1a0c001 MOV r12, r10x30200f30 0x00000000 ANDEQ r0, r0, r00x30200f34 0xe2522020 SUBS r2, r2, #0x200x30200f38 0xa8a0500a STMGE r0!, {r1, r3, r12, r14}0x30200f3c 0xa8a0500a STMGE r0!, {r1, r3, r12, r14}0x30200f40 0x00000000 ANDEQ r0, r0, r00x30200f44 0xa8a0500a STMGE r0!, {r1, r3, r12, r14}
It'd be nice to know if this code also works on Clipv2
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